Above: Lizhong Chen, Fawaz Alazemi and Bella Bose.

A team of Oregon State University researchers in the School of Electrical Engineering and Computer Science have developed a technology that improves the communication between cores of a computer chip, which can boost performance and energy efficiency. The new network-on-chip (NoC) technology was developed by Lizhong Chen, an assistant professor of electrical and computer engineering, in collaboration with Bella Bose, professor and senior associate school head, and graduate student Fawaz Alazemi.

Cores — independent processing units that calculate and execute computer program instructions — communicate with one another to share data. Most of the computers and devices we use today — including desktops, laptops, tablets and cell phones — use multi-core processor technology. The number of cores has a big impact on processing speed, but how they communicate is also an important factor.  

Understanding typical core systems

Most computers and electronic devices today use either a bus-based or a router-based structure for connecting cores in a processor.

Bus-based processors

Bus-based is the simplest core system. It includes a collection of wires that connect each core to the next. The cores transfer data one at a time to the neighboring core. Because the communications take place one at a time, the bus system works best with fewer cores (around 10). If you were to attach 100 cores in a bus system, the communication would be very slow because of the long distance between the cores and the large capacitive load on the bus.

Router-based processors

A router-based system is much faster than a bus-based system. In this setup, each core is attached to a router (a small block that can direct communication). The routers are connected to one another through a series of wires, similar to a traffic grid. The main benefit of a router-based system is it allows for a larger number of cores and multiple communications at one time, like a traffic grid with multiple cars driving at once. The disadvantage is it is much more costly to produce than a bus-based system due to the large overhead of chip area and the power consumption of the routers.

Routerless Network-on-Chip (NoC) technology

Chen’s technology, called routerless network-on-chip (NoC), achieves the benefits of both approaches by eliminating the need for routers. This routerless design is composed of layers of wires, each of which is strategically placed to connect a series of cores with minimal distance. This new NoC technology has the simplicity of a bus-based system and the speed of a router-based system. Without including routers, chip manufacturers have more die area to incorporate a larger number of cores, leading to higher computing capacity. In addition, the accelerated communication between cores helps to significantly achieve higher overall performance. The overhead in manufacturing the NoC is also much lower than a router-based system.

The routerless NoC is geared toward any company that builds its own computer chips. The technology serves as a guide that chipmakers can follow to create a design that is low-cost, fast and communicates effectively.

Chen has obtained a provisional patent for his technology, and his goals include getting additional funding for his research and potentially licensing the routerless NoC to a microprocessor manufacturer. This winter, Chen and his team plan to submit a research paper to the prestigious International Symposium on Computer Architecture (ISCA). If accepted, it will be the first paper solely developed from Oregon State to be shared at this top computer architecture venue.

For licensing information, please contact David Dickson at david.dickson@oregonstate.edu or 541-737-3450.